Site Loader

View the profiles of people named Laurent Souef. Join Facebook to connect with Laurent Souef and others you may know. Facebook gives people the power to. Semantic Scholar profile for Laurent Souef, with fewer than 50 highly influential citations. Family tree Laurent Souef.

Author: Dugrel Taushakar
Country: Maldives
Language: English (Spanish)
Genre: Environment
Published (Last): 15 March 2015
Pages: 365
PDF File Size: 10.5 Mb
ePub File Size: 3.22 Mb
ISBN: 885-5-44894-214-8
Downloads: 6255
Price: Free* [*Free Regsitration Required]
Uploader: Meztilkis

Thus, no power consumption of such stages takes place during functional operation. The IC further comprises a test arrangement for testing the respective clusters of switches ; in a test mode. The invention relates to a testable integrated circuit. Design for test area optimization algorithm. The test arrangement comprises a test control input; a test output coupled to the respective internal supply rails and control means, coupled to the test control input for enabling a selected cluster of switches ; in the test mode.

The output response of the integrated circuit to the test vector is provided under the control of a second clock signal 56 which is slower than the first clock signal.

Cell with fixed output voltage for integrated circuit. These means for setting the output voltage are controlled by a control signal 15 which depends on the mode signal that indicates whether the signal is in the test mode or in the operation mode. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.

Computer implemented circuit synthesis system. The row drive provides a current input for the column drive in one phase of operation and the column drive provides a current input for a row drive in a second phase of operation. Method of discriminating between different types of scan failures, computer readable code laufent cause a display to graphically depict one or more simulated scan output data sets versus time and a laurrent implemented circuit simulation and fault detection system.


Existing ATPG tools may be used without modification by performing scan insertion on a “dummy” circuit and performing ATPG on the scan-augmented dummy circuit. Frederic Natali, Laurent Souef. Koninklijke Philips Electronics N. Patrick Da Silva, Laurent Souef. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set.

Pseudo-scan testing using hardware-accessible IC structures. Each cluster of switches ; has a first switch having a first size and a second switch having a second size, a fault-free first switch having a higher resistance than a fault-free second kaurent The row drive and the column drive are in a low conductive condition except when a relevant key switch is activated.

Laurent Souef

suoef Laurent Souef, Didier Gayraud. Method of testing an integrated circuit by simulation. The test program extracts the simulated scan flops and graphically displays the simulated scan flops versus time. The present invention, generally speaking, provides an integrated circuit testing technique in which hardware accessibility of selected components is exploited in order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used.

Laurent Souef Inventions, Patents and Patent Applications – Justia Patents Search

In the scan test mode, the counter operates as a shift register and it is fully testable. Jerome Bombal, Laurent Souef.

An integrated circuit is disclosed comprising a plurality of circuit portionseach of the circuit portions having an internal supply rail coupled to a global supply rail via a cluster of switches ; coupled in parallel between the internal supply rail and the global supply rail Furthermore, the method can be implemented without requiring additional complexity of the testing circuitry to be integrated onto the circuit substrate.

The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low.

Clock-skew resistant chain of sequential cells. Laurent Souef has filed for patents to protect the following inventions. The automatic test pattern generation ATPG algorithm is operative to design and test an integrated circuit design.


A key handling circuit for a switching matrix having row and column conductors includes bidirectional drives for the row conductors and the column conductors. A method of discriminating between different types of simulated scan failures includes simulating a scan enable signal to a circuit represented by a netlist corresponding to a scan chain coupled to combinatorial logic being tested, simulating initiation of a data capture cycle in the netlist corresponding to the scan chain, the data capture cycle simulating a series of scan flops from the scan chain being simulated together with the combinatorial logic and simulating scanning data out from each flop in the lauurent chain and into a test program.

Low power scannable counter.

dblp: BibTeX records: Laurent Souef

This testing method speeds up the process by increasing the speed of shifting test vectors and results into and out of the shift register, but without comprising the stability of the testing process. A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement 20 timed with a first, scan, clock signal In an integrated circuit incorporating a series of sequential cells SEQ 1 -SEQ 7 implementing a shift function, clock skew problems are avoided by interconnecting the cells in order starting with the cell SEQ lurent having greatest clock latency laurrnt ending with the cell SEQ 7 having smallest clock latency.

The term “pseudo-scan” is used to refer to the use of read and write instructions to achieve siuef equivalent effect as scan insertion without the addition of scan flops.